Observations & Opportunities: Nanoscale Challenges As Chipmakers Produce ICs with 10nm & 7nm Features

Remember the sub-micron-featured ICs in PCs just a few decades ago? That was doable. Some chipmakers did complain a bit about technical challenges as they retooled for smaller-featured optical lithography requirements (180nm, 90 nm, 65 nm, 45 nm, 32 nm, etc.) and more demanding processing but they all knew they could make it work, profitably. With 10nm or smaller, however, profitability is and manufacturing are more challenging technology leaps. This Blog explores some emerging IC and MEMS manufacturing advances and challenges.

The Bleeding Edge
The world’s most demanding and sophisticated high-volume thin-film deposition occurs during the wafer fabrication of nano-scaled ICs and some MEMS devices. MEMS (Micro-Electro-Mechanical Systems) typically are a few generations behind ICs smaller critical dimensions but the MEMS devices are increasingly used in mission-critical applications which demands precision and repeatability. MEMS must provide that requisite physical interface to the world on micro and nano scales. Since MEMS incorporate electrical and/or optical I/Os and/or other electronic circuitry, this obviously impacts design and manufacturing efforts.

Remember the “Hype Cycle for Emerging Technologies, 2017” from Gartner Inc.[1]. Here it is again below. Consider that virtually none of these anticipated high-growth market opportunities will be possible without more computing power in ever smaller packages and that increasingly includes AI (Artificial Intelligence) to enable previously unattainable results. To get this performance, chipmakers and computer makers need faster processors and more memory, the latter preferably being fast and rugged. One given: vacuum-enabled thin-film processing for deposition, plasma etching and cleaning demands will be tougher than ever.

The hype cycle for emerging technologies. Source: Gartner Inc., Stamford, CT


We’ve all heard about the options being evaluated when silicon ICs can no longer do the job. Nanosheets and carbon nanotube transistors are possibilities but this is an industry that usually resists change in its wafer fabrication processes. That does not mean they won’t do it if necessary. There is also the requisite support infrastructure needed to maintain and tweak process machines for ≤10nm production.

Parallel Production
It will take years to transition from mainstream IC manufacturing to EUV lithography and even longer if non-silicon devices are used. But ≤10 nm devices will not lessen the need for currently maxed out existing optical lithography wafer fabs that will likely keep producing “standard” ICs and MEMS for decades since those devices will be needed for mainstream applications. Recently, more 3D deices with many layers help cram more into chips.

The emerging ≤ 10nm generation is beyond most chipmaker’s comfort zones. We’ll explore some of the challenges these semiconductor manufacturers face as early production of chips with feature sizes at 10nm and 7nm begins, perhaps using EUV lithography, if it is ready, or pushing forward with older but proven familiar lithography technology awaiting EUV reality with high wafer-per-hour throughputs.

Now a nomenclature caution: chipmakers are being creative with marketing terminology when it comes to exact “nodes” that they are actually using now, what is planned and with 10nm or 7nm claims are not being truly comparable. “Node” being a somewhat vague way of describing “industry standard” references to the geometries being fabricated. The bottom line: feature sizes are shrinking one way or another so producing more transistors per mm2 is a given.

Mark Bohr is an Intel Senior Fellow and director of process architecture and integration at Intel Corporation. During the recent Technology and Manufacturing Day presentations, pointed out Intel’s innovation enabled technology pipeline carries through to 7nm, 5nm and 3nm feature sizes.

Intel’s innovation enabled technology pipeline.


Clearing Up the Node Naming Mess
Bohr posits, “Let’s clear up the node naming mess. Moore’s Law, as stated by our co-founder over half a century ago, refers to a doubling of transistors on a chip with each process generation. Historically, the industry has been following this law, and has named each successive process node approximately 0.7 times smaller than the previous one – a linear scaling that implies a doubling of density. Thus, there was 90 nm, 65 nm, 45 nm, 32 nm – each enabling the packing of twice the number of transistors in a given area than was possible with the previous node.

“But recently – perhaps because of the increasing difficulty of further scaling – some companies have abandoned this rule, yet continue to advance node names, even in cases where there was minimal or no density increase. The result is that node names have become a poor indicator of where a process stands on the Moore’s Law curve.”

“Every chip maker, when referring to a process node, should disclose its logic transistor density in units of MTr/mm2 (millions of transistors per square millimeter) as measured by this simple formula. Reverse engineering firms can readily verify the data.

Intel Transistor Density Formula


“There is one important measure missing: SRAM cell size. Given the wide variety of SRAM-to-logic ratios in different chips, it is best to report SRAM cell size separately, next to the NAND+SFF density metric.

“By adopting these metrics, the industry can clear up the node naming confusion and focus on driving Moore’s Law forward,” added Bohr.

Intel’s 10nm
Before the Consumer Electronics Show (CES 2017) began, Intel Corp. kicked off the event with announcements in automated driving, 5G technologies and virtual reality — or the more advanced merged reality.

“The pace of technology improvement is accelerating faster than ever,” said Intel CEO Brian Krzanich. “Moore’s Law is at the center of this acceleration. Technology is extending far beyond consumer electronics, defining almost every aspect of our lives, and transforming industries.”

Krzanich described the company’s vision for VR and merged reality technology and how these technologies will reinvent the experiences of travel, work safety and productivity, and sports and gaming. He explained that Intel’s first 10nm-powered 2 in 1 PC with Intel’s next generation processor, codenamed Cannon Lake, made it possible. Intel’s Cannon Lake 10nm technology is said to have the world’s tightest transistor and metal pitches, created with hyper scaling, for the highest density in the industry.

Intel’s Cannon Lake 10nm technology is said to have the world’s tightest transistor and metal pitches


During Intel’s Technology and Manufacturing Day last year, Kaizad Mistry, Corporate Vice President, Technology and Manufacturing and Co-Director, Logic Development, said that Intel’s 10nm technology is a full generation ahead of other “10nm” processes. Mistry added, “Hyper scaling extracts the full value of multi-patterning schemes and and allows Intel to continue the benefits of Moore’s Law economics.”

2018—The Year of 10nm Critical Dimensions and EUV Lithography
From several published reports over the past year, 2018 is the year of ≤10nm with EUV (Extreme UltraViolet) but we’ve heard that before.

There are just a handful of chipmakers now who can afford the new 10nm, 7nm and smaller lithography equipment. Taiwan Semiconductor Manufacturing Company (TSMC) is challenging Samsung Electronics in the race for ≤7nm process volume production in 2018. TSMC has many orders for fabricating chips with 7nm processing for mobile communications, high-performance computing and AI (artificial intelligence) applications. Apple and Qualcomm are among TSMC’s major customers, with the foundry house contracted to fabricate all the advanced Apple A12 processor chips for the 2018 next-generation iPhones. TSMC will use extreme ultraviolet (EUV) technology for its 7nm+ process and step up EUV deployments in the 5nm and 3nm processes. TSMC will outpace Samsung in 7nm volume production in 2018.

TSMC is building a 5nm production fab (Fab 18) in the Southern Taiwan Science Park this year. It will also invest US$20 billion on a 3nm fab in the park, with construction starting in 2020. Their 5nm process will be an extension of its 7nm process, targeting mobile communication, high-performance computing, AI, and machine learning (ML) applications.

Samsung is building a 7nm production line in Hwaseong, Korea. The company is negotiating with U.S. and Chinese customers over new projects. Samsung spun off its wafer foundry as an independent business unit in 2017. It will launch 4nm processing in 2020 against TSMC’s 5nm node, before starting volume production of 7nm process in 2018 and developing 6nm and 5nm processes in 2019, according to sources.

Samsung says it will start manufacturing chips with circuitry widths of 7nm by using EUV tech in the second half of 2018. TSMC also said hat its chip manufacturing process using EUV technology will be the “most advanced technology in foundry industry” in 2018 in terms of density, performance and power.

Meanwhile, GLOBALFOUNDRIES’ new 7LP 7nm FinFET process technology targets high-performance, power-efficient System-on-Chips (SoCs) for demanding, high-volume applications. This provides world-class performance, power, area and cost advantages through 7nm scaling. Based on a 3D FinFET transistor architecture imaged with optical lithography but it is EUV compatible where needed. 7LP delivers more than twice the logic and SRAM density, and either >40% performance boost or >60% total power reduction, compared to 14nm foundry FinFET offerings.

GLOBALFOUNDRIES 7LP 7nm FinFET process technology platform produces high-performance, power-efficient SoCs in demanding, high-volume applications


With 100 million transistors per square millimeter density, or more, being normal now, the world’s most demanding and sophisticated high-volume thin-film deposition requirements during wafer fabrication of ICs and MEMS devices only get more demanding. Wafer fabrication toolmakers must continue to refine their machines, perhaps even including AI at some point to handle new data requirements and process variations needed by customers. With the high stakes for all involved, every process must be exceedingly accurate and repeatable.

1. Terrence Thompson, Vacuum Technology & Coating, “Faster Changes and the Implications” blog, August 2017, posted on Aug. 23, 2017, Observations & Opportunities.
2. Steve Hansen, Vacuum Technology & Coating, Vol. 18, No. 2, Feb. 2017, “Miniature Analyzers and IonTraps From Compact to MEMS”, pp. 12-16.
3. Donald M. Mattox, Vacuum Technology & Coating, Vol. 5, No. 12, Dec. 2004, SVC Educational Guide, “Applications: Low-Pressure CVD and PECVD: Plasma-Enhanced Chemical Vapor Deposition (PECVD)”, pp. 28-30.

Note: The many vacuum-centric deposition, coating, etching and cleaning processes that Vacuum Technology & Coating has covered recently, as well as those going back almost 15 years, are worth exploring. These articles serve as invaluable basic primers while others describe leading-edge applications. These are free articles, and magazine issues, to peruse and educate. Visit http://www.vtcmag.com and explore the magazine’s online viewing or downloadable PDF issues. Use the Search button to find specific topics.

Next time: We’ll take a look at some new MEMS sensors and why they are essential.