Vacuum Observations & Perspectives

In this weblog series, we’ll examine some emerging and evolving opportunities for vacuum-centric equipment, materials, processes and R&D. Also, we’ll look at some interesting applications and technology trends. Thinking outside the box, if you will, with a broad perspective.

Vacuum use is only likely to increase going forward, especially when producing very small and complex components like ICs and MEMS for sophisticated products. Doing so in a vacuum is the only practical way to prevent gaseous and particulate contamination. Vacuum is absolutely essential for semiconductor production.

Semiconductor Challenges—Manufacturing Is Difficult

The familiar semiconductor industry is changing, significantly, now. These changes provide many opportunities for those companies involved that can meet the challenging technical and investment demands. The microchip industry itself is always continuing its quest for ever smaller geometries (circuit features) to get more devices produced per wafer area. That’s how Moore’s Law has keep innovation and performance increases alive.

By constantly pushing new frontiers of equipment, materials, and processes, chipmakers produce the ubiquitous integrated circuit (IC) chips at reasonable prices. Historically, jumps in wafer size were tied to photolithography advances that enabled smaller feature sizes. The result was more advanced semiconductor chips with greater performance. Transistors are much smaller now and circuits more complex but greater performance results. But they are extremely difficult to manufacture.

The greatest demand for computer chips now is in mobile devices, wireless, IoT and automotive areas. Laptops, tablets and smartphones all benefit. Since desktop PC performance is already greater than what most customers actually need, mobile devices are often a primary focus. For products where space and extreme performance are not necessary, conventional IC manufacturing fabs will be cranking out those chips for years. You certainly don’t need state-of-the-art microprocessors in your home’s thermostat.

Monolithic ICs

Semiconductor manufacturing, often considered a mature industry, needs near-perfect thin films and truly advanced lithography patterning along with sophisticated deposition and etching process technologies to produce the active and passive elements in ICs—the core of most high tech products worldwide. Planar 2D production is mainstream now in semiconductor manufacturing but some high-profit, in-demand chips are now made with 3D circuitry. Conventional optical photolithography now appears to be at the end of its affordable smaller dimensions potential but there is a promising new exposure system: EUVL.

2D, 3D & EUV Lithography

To produce more chips in the same wafer surface space, you need smaller chips that provide the functionality but in smaller dimensions. Greater functionality and faster performance are the norms. If the latest EUVL (Extreme UltraViolet Lithography) tools prove ready for prime time with high-volume production next year, the quality and flatness of the many deposited thin film layers will become even more critical than they are now. EUV needs a stringent vacuum environment. See “THE USE OF EUV LITHOGRAPHY IN CONSUMER MICROCHIP MANUFACTURING” at http://www.pitt.edu/~budny/papers/23.pdf for some insights.

In July 2017, ASML Holding N.V. (ASML) President and Chief Executive Officer Peter Wennink said, “In EUV lithography, we have integrated an upgraded EUV source into a TWINSCAN NXE:3400B lithography system in our Veldhoven [The Netherlands] facility and achieved the throughput specification of 125 wafers per hour on this system. Now, with all key performance specifications demonstrated, we focus on achieving the availability that is required for high-volume manufacturing as well as further improving productivity.”

That sounds promising but the actual EUV masks and photoresists seem somewhat problematic from published comments and reports. In July 2017, BACUS (formerly the Bay Area Chrome Users Society) noted, “Recently, readiness of the EUVL infrastructure for the high volume manufacturing (HVM) has been accelerated [1]. EUV source availability, the first showstopper against EUVL HVM, has been dramatically increased and close to the targets for HVM insertion. Mask defectivity, another focus area for the HVM, has also been concerned. Due to the difference in mask and optics appropriate for the wavelength between EUV and ArF lithography, specialized metrology tools are required in EUVL. However, current DUV and e-beam inspection tools are easy to miss the printable phase defects in EUV mask since the lights of corresponding wavelengths cannot penetrate multilayers (MLs)[2,3]. Therefore, the actinic review system is essential to provide defect free EUV masks.” See more details at https://spie.org/Documents/Membership/BacusNewsletters/BACUS-Newsletter-July-2017.pdf

The Samsung R&D experts who authored this are betting on EUV and 7nm lithography to take some IC foundry business away from the leading foundry producer TSMC (Taiwan Semiconductor Manufacturing Co.) but TSMC is also planning on introducing 7nm EUV devices next year. We’ll see. EUV keeps getting promised as “soon” but the dates keep slipping. Reuters noted, “But the firm lags well behind Taiwan’s TSMC in contract manufacturing: TSMC held a market share of 50.6 percent last year compared with Samsung’s 7.9 percent, according to research firm IHS. It also trailed U.S.-based Global Foundries, which had a 9.6 percent share, and Taiwan-based UMC’s 8.1 percent.”

Wafer Sizes Matter

First, there are wafer size considerations. Today, 200mm wafer fabs are typically running at capacity with some new 200mm fabs being built but some essential 200mm fabrication production tools are in short supply and expensive. Some of these fabs once made high-volume state-of-the-art ICs but have transitioned to more profitable proprietary and/or lower volume chips. Supporting 200mm will be necessary for the foreseeable future.

Per Christian G. Dieseldorff, Industry Research & Statistics Group, SEMI, at SEMICON West 2017, “Driven by mobile and wireless applications, IoT (Internet of Things), and automotive, the 200mm market is thriving.  Many of the products used in these applications are produced on 200mm wafers, so companies are expanding capacity in their facilities to the limit, and there are nine new 200mm facilities in the pipeline. Looking only at IC volume fabs, the report shows 188 fabs in production in 2016 and expanding to 197 fabs by 2021. China will add most of the 200mm capacity through 2021, with 34 percent growth rate from 2017 to 2021, followed by South East Asia with 29 percent and the Americas with 12 percent.”

The 300mm fabs, once expected to displace 200mm fabs, are now competing with 200mm in some markets where smaller volumes can make 300mm efforts more expensive. But 300mm is running at capacity too with the most advanced chips. There also has been the realization by the major semiconductor manufacturers that many improvements to optimize 300mm manufacturing are possible which delays the costly transition to building factories that handle 450mm wafers.

Finally, 450mm seems to be a wafer size that can wait, perhaps until 2020 per SEMI [http://www.semi.org/en/node/50856]. Also, the New York-based 450mm global consortium, G450C, is defunct. Samsung, and others, are now stacking many layers of transistors on the same memory die with smaller transistors, so the need for 450mm wafers is not as urgent now although companies are still exploring 450mm options for the future.

Then, of course, there is the high-end leading edge efforts to switch to EUV lithography in the quest to produce even more ICs per unit area on a wafer. EUV emerged when x-ray proved problematic years ago. X-ray lithography was first proposed by H. Smith and Spears at MIT. [https://www.researchgate.net/publication/299496830_X-ray_Lithography_Some_History_Current_Status_and_Future_Prospects]. There are recollections of the frantic x-ray lithography efforts several years ago that never reached mainstream production status. X-ray lithography promised > 1nm feature sizes, far smaller than the EUV efforts of today will produce.

Mainstream x-ray lithography simply had too many issues at the time: dangerous x-ray sources as well as expensive masks and resists that were problematic. Proposed x-ray synchrotron radiation sources required very long times to reach acceptable low vacuum levels which is problematic for volume production lines that cannot stop operating for maintenance. For some perspective on x-ray lithography’s origins, check out “X-ray lithography: Some history, current status and future prospects” by Juan R. Maldonado and Martin Peckerarat https://www.researchgate.net/publication/299496830_X-ray_Lithography_Some_History_Current_Status_and_Future_Prospects.

Note: Upcoming weblogs will address IC lithography issues and why MEMS devices are essential in mobile devices and many other products.